Conventionally, as a type of synchronous semiconductor devices, SDRAM (Synchronous Dynamic Random Access Memory) has been known. According to a known technique, an input buffer is so configured that a SDRAM receives a clock enable signal (i.e., a clock control signal) with a clock signal and inputs the clock signal only when the clock enable signal is activated, thus achieving reduction of power consumption (see Patent Reference 1).
There is also a known technique in which a gate voltage of an output switching device is boosted up using a delay circuit and a capacitor at start-up of an output circuit to temporarily enhance an output current of the output switching device (see Patent Reference 2).    Patent Reference 1: Japanese Laid-Open Publication No. 2000-36192    Patent Reference 2: Japanese Laid-Open Publication No. 2-238709